Integrated circuits typically comprise semiconductor devices, such as bipolar junction transistors (BJTS) and metal-oxide semiconductor field effect transistors (MOSFETS) formed from doped regions within a semiconductor layer or substrate. Interconnect structures overlying the substrate connect the BJTS and MOSFETS to form circuits. The interconnect structures comprise conductive runners or traces alternating with dielectric layers. Conductive vias disposed in the dielectric layers connect overlying and underlying conductive runners and traces.
BiCMOS integrated circuits comprise both bipolar junction transistors and CMOS (complementary metal oxide semiconductor field effect) transistors with the fabrication process steps for both devices integrated into one fabrication sequence. Integrating BJTS and MOSFETS on the same integrated circuit die allows the circuit designer to take advantage of both the BJT advantages of high speed and high frequency operation and the MOSFET advantages of low power consumption, high noise immunity and small die area.
The overall process sequence and the individual process steps (e.g., implanting dopants, depositing and patterning material layers, forming openings, epitaxially growing material layers, forming interconnect structures) must be carefully designed and executed to ensure that the process steps for forming the BJTS do not adversely affect the MOSFETS and vice versa, as such adverse effects can lower fabrication yields and increase costs. Thus semiconductor manufactures desire to implement a BiCMOS process flow for fabricating properly operable BJTS and MOSFETS on the same die with a high fabrication yield.
According to conventional BiCMOS processes, a BJT emitter is formed from a polysilicon material layer deposited in an emitter window. First a hard mask layer is formed overlying the emitter polysilicon layer and patterned. The polysilicon layer is etched according to the patterned hard mask and the hard mask is removed. During polysilicon etching the hard mark layer thickness is gradually reduced and the etch process is terminated when the etchant reaches the emitter polysilicon layer. However, during etching an upper region of the emitter polysilicon layer may be consumed, possibly impairing device functionality since a minimum emitter polysilicon thickness is required for proper operation. In an extreme case the bipolar junction transistor can be rendered nonfunctional by excessive erosion of the polysilicon emitter layer.
Known techniques to overcome the effects of emitter layer erosion include forming a thicker polysilicon emitter layer such that notwithstanding erosion the layer is sufficiently thick to present an acceptable resistance. Disadvantageously, this technique increases the stack height of the bipolar junction transistor material layers. Also, it is more difficult to etch a thicker polysilicon layer to form the required emitter region shape.
After forming the BJT emitter, the fabrication sequence forms MOSFET source and drain regions by implanting dopants into the substrate. The substrate is then annealed to repair crystal lattice damage resulting from collisions between the implanting dopants and the lattice atoms and to electrically activate the implanted dopants (i.e., to transfer the implanted dopant atoms from an interstitial to a substitutional state within the silicon crystal). A rapid thermal anneal (at about 1000° C. for about 20 seconds) is required for dopant activation. During the activation process, dopants in the emitter polysilicon tend to out-diffuse to the adjacent base, reducing the effectiveness of the BJT and potentially causing device failure.
It is known to reduce the duration and/or the temperature of the thermal anneal step to reduce dopant out-diffusion, but device functionality may be compromised if the dopant atoms are not completely activated.